1. Technical Field
The present invention relates to an apparatus and method for an I/O circuit, in particular to an apparatus and method for serial to parallel in an I/O circuit.
2. Description of the Prior Art
In general, the number of pins of an IC is fixed after being manufactured. In the meantime, because of the trend of an SOC (system on a chip), a part of the pins must be shared so as to achieve an object of reducing IC size. Therefore, under the limitation of pin counts and the trend of SOC, it is an inevitable result that a single pin has multi-functions.
As shown in FIG. 1, a pin of an IC designed by using the concept of a single pin with a multifunction can possess many functions simultaneously, but at one time only a function can enable (i.e., the pin can be used by selecting only one of those functions each time). Thus a next function will not be shifted to until the present function is completed. Its speed is slower than that of an IC without any multifunction pin, and therefore is only suitable for use in a relatively slow bus. In addition, an additional pin as a chip select should be provided for function switching in the above architecture.
Generally, in order to overcome the advantage of insufficient output pins, such a way of a sequential logic circuit (as shown in FIG. 2A) may be used to extend pins. An I/O circuit can be formed by combining a plurality of sequential logic circuits, and each of which can process one bit of data. If there is a need to increase the number of outputs, it only needs to increase the number of the sequential logic circuits (as shown in FIG. 2B). Each sequential logic circuit comprises a D-type flip-flop and a D-type latch. For an M-bit input data stream I (I0 . . . IM−3IM−2IM−1), one bit of the input data is input into the D-type flip-flop of the first sequential logic circuit each time in accordance with the bit sequence thereof. After the D-type flip-flop receives a set of input data, it will transfer the previously received input data to a next stage D-type flip-flop. When the input of data stream I (I0 . . . IM−3IM−2IM−1) is completed, triggered by a clock signal CLK, the written input data stream I (I0 . . . IM−3IM−2IM−1) is output to a corresponding D-type Latch for latching. Finally, triggered by another clock signal Load, the data stream I (I0 . . . IM−3IM−2IM−1) is outputted, where M is greater than or equal to the number of the sequential logic circuits.
For example, FIG. 2C shows an 8-bit I/O circuit 200, which includes 8 sequential logic circuits. Firstly, the D-type flip-flop D0 of a first sequential logic circuit 210 receives a first set of input data I0 of a M-bit input data stream I (I0 . . . IM−3IM−2IM−1) (M>=8) as its input data. Thereafter, when a second set of input data I1 is input into the first D-type flip-flop D0, I0 is sent to the D-type flip-flop D2 of the second sequential logic circuit 220 as its input data. Then, after a third set of input data I2 is input into the first D-type flip-flop D0, I1 is sent to a second D-type flip-flop D1 while I0 is transmitted to a third D-type flip-flop D2, . . . etc. After the input of all the data stream I (I0 . . . IM−3IM−2IM−1) (M>=8) is completed, being triggered by the clock signal CLK, the input data are outputted to corresponding D-type latches (for example, the first D-type flip-flop D0 corresponds to a first gating latch DG0), respectively, and the corresponding gating latches latch their input data, respectively. Finally, being triggered by a clock signal Load, all the input data stream I (I0 . . . IM−3IM−2IM−1) (M>=8) are outputted simultaneously. Before the input data stream I (I0 . . . IM−3IM−2IM−1) (M>=8) is written in, a clear signal CLR may be used to clear out the input data written previously in the D-type flip-flops. As can be seen from the input and output statuses in FIG. 7, the system will not output data until it is written in at least 8 bits.
FIG. 3 shows an operational flowchart of an existing I/O circuit, and the steps of which are described as follows:
Step 310: a clear signal CLR is inputted to clear out the input data written previously;
Step 320: the input data stream I (I0 . . . IM−3IM−2IM−1) (M>=8) is input into the first D-type flip-flop one bit each time in order of bit, and when a next set of input data are inputted, the previous set of input data will be pushed to a next stage D-type flip-flop;
Step 330: after the input of the data stream I (I0 . . . IM−3IM−2IM−1) (M>=8) is completed, triggered by the clock signal CLK, the input data are outputted to corresponding D-type latches for latching, respectively; and
Step 340: triggered by the clock signal Load, the input data stream I latched by the D-type latch is output.
As can be seen from the above descriptions, the sequential logic circuits are designed with additional output pins in a series connection manner so as to overcome the problem of insufficient output pins in an IC. However, the output will not be performed until all the sequential logic circuits are fully written in each time, which might affect the whole system performance because of slow data transmission rate.